The field of the invention is that of integrated circuit fabrication, in particular forming fully silicided field effect transistors without the use of CMP.
The field of integrated circuit fabrication has benefited greatly from the use of chemical-mechanical polishing (CMP), which has become part of the standard processing sequence.
The improved planarity provided by CMP has permitted the use of steppers with very high numerical apertures and with consequently very small depth of focus. In addition, the improved planarity has reduced defects caused by step height differences.
Quality standards have increased as time has passed and scratches and other defects caused by the CMP process have become a significant yield detractor.
One example is the variation in the height of the poly transistor gates, which cause variation in the quality of suicides formed on the gates and Vt scattering caused by the dopant snowplow effect.
In the course of a conventional process to fabricate a planar field effect transistor, the transistor structure of gate bracketed by sidewalls and embedded in the first level ILD is planarized with CMP to establish a plane at the level of the top of the gate so that the polysilicon gate can be silicided. Vertical conductors pass through this plane in order to establish contact between the electrodes of the transistors and higher level interconnect structures.
Grooves in the material that forms this plane can become filled with conductor material and establish short circuits.
The art could benefit from a method of forming a planar (silicided) field effect transistor that does not use CMP.